library ieee;
use ieee.std_logic_1164.all;

entity HALF_ADDER is
port(	
    A,B:	in std_logic;
	SUM,CO:	out std_logic
);

end HALF_ADDER;

architecture behv of HALF_ADDER is
 
begin	
    SUM <= A xor B;
    CO <= A and B;

end behv;